Dual Core 32-bit Processor Design
Last week, while attending the Embedded Systems Conference, I needed to get going on my dual core cpu design for my semester project (which is tied into my thesis). Using Xilinx's Microblaze IP core, I was able to design the following system that consists of a shared memory architecture for the two microblaze processors to communicate with. The on board cache consists of 4KB of data and 2KB of instruction per processing element. The objective of the design is to create a cache coherent system utilizing one of the many protocols available that monitor the integrity of the data across the two systems. The primary issue at hand is that when utilizing a shared memory architecture, it's very likely that one processor might use the same variable that the other processor is using. In this case, the processor would utilize the mutex lock (see diagram) to prevent the other processor from using it during it's operation. Once the processor is finished, it'll release the lock and more than likely leave the page in it's cache in a "dirty" state. This means that it's modified in it's own cache, but it has yet to be written back to the shared memory. When processor 2 accesses that variable in shared memory, it'll be using an outdated, or older copy that doesn't reflect the correct result that processor 1 just posted in it's own cache. This is where my project comes into play. Somehow, I need to create an intermediary that will determine where the most current state of that variable resides and then provide that to the requesting processor. More to come later on the MSI protocol.
Kor
